Literature Survey of 12 Bit Pipe Line Analog to Digital Converter

Optimal fast digital error correction method of pipelined analog to digital converter with DLMS algorithm

In this paper, convergence rate of digital error correction algorithm in correction of capacitor mismatch error and finite and nonlinear gain of Op-Amp has increased significantly by the use of DLMS, an evolutionary search algorithm. To this end, a 16-bit pipelined analog to digital converter was modeled. The obtained digital model is a FIR filter with 16 adjustable weights. To adjust weights o...

14-Bit 1MS/s Cyclic-Pipelined ADC

This paper presents a 14-bit cyclic-pipelined Analog to digital converter (ADC) running at 1 MS/s. The architecture is based on a 1.5-bit per stage structure utilizing digital correction for each stage. The ADC consists of two 1.5-bit stages, one shift register delay line, and digital error correction logic. Inside each 1.5-bit stage, there is one gain-boosting op-amp and two comparators. The A...

A 1.8V 12-bit 1GS/s SiGe BiCMOS time-interleaved Analog-to-Digital converter

Improving adaptive resolution of analog to digital converters using least squares mean method

This paper presents an adaptive digital resolution improvement method for extrapolating and recursive analog-to-digital converters (ADCs). The presented adaptively enhanced ADC (AE-ADC) digitally estimates the digital equivalent of the input signal by utilizing an adaptive digital filter (ADF). The least mean squares (LMS) algorithm also determines the coefficients of the ADF block. In this sch...

A Quick Primer on Complex Numbers

The physical layer is the lowest layer in the OSI network hierarchy. The services provided by this layer include digital-to-analogue conversion, modulation, demodulation, and analogue-to-digital conversion. From a vantage point higher up in the OSI hierarchy, the physical layer provides a virtual bit pipe for the transmission of information. Imperfections and perturbative noise in the channel, ...